ROCm 6.3.2 also adds support for Azure Linux 3.0 (kernel: 6.6), which is only supported on AMD Instinct accelerators. Key changes to ROCm components include tracking of Heterogeneous System Architecture (HSA) handlers, optimizing HSA callback performance, multi-threaded dispatches for performance improvement, and switching to std::shared_mutex in book/keep logic in streams from multiple threads simultaneously.
ROCm 6.3.2 Release
Release highlights
The following are notable improvements in ROCm 6.3.2. For changes to individual components, see
Detailed component changes.ROCm documentation updates
ROCm documentation continues to be updated to provide clearer and more comprehensive guidance for a wider variety of user needs and use cases.
Documentation about ROCm compatibility with deep learning frameworks has been added. These topics outline ROCm-enabled features for each deep learning framework, key ROCm libraries that can influence the capabilities, validated Docker image tags, and features supported across the available ROCm and framework versions. For more information, see:
The HIP C++ language extensions and Kernel language C++ support topics have been reorganized to make them easier to find and review. The topics have also been enhanced with new content.
Operating system and hardware support changes
ROCm 6.3.2 adds support for Azure Linux 3.0 (kernel: 6.6). Azure Linux is supported only on AMD Instinct accelerators. For more information, see Azure Linux installation.
See the Compatibility
matrixfor more information about operating system and hardware compatibility.ROCm components
The following table lists the versions of ROCm components for ROCm 6.3.2, including any version
changes from 6.3.1 to 6.3.2. Click the component's updated version to go to a list of its changes.
Click {fab}github
to go to the component's source code on GitHub.Detailed component changes
The following sections describe key changes to ROCm components.
HIP (6.3.2)
Added
- Tracking of Heterogeneous System Architecture (HSA) handlers:
- Adds an atomic counter to track the outstanding HSA handlers.
- Waits on CPU for the callbacks if the number exceeds the defined value.
- Codes to capture Architected Queueing Language (AQL) packets for HIP graph memory copy node between host and device. HIP enqueues AQL packets during graph launch.
- Control to use system pool implementation in runtime commands handling. By default, it is disabled.
- A new path to avoid
WaitAny
calls inAsyncEventsLoop
. The new path is selected by default.- Runtime control on decrement counter only if the event is popped. There is a new way to restore dead signals cleanup for the old path.
- A new logic in runtime to track the age of events from the kernel mode driver.
Optimized
- HSA callback performance. The HIP runtime creates and submits commands in the queue and interacts with HSA through a callback function. HIP waits for the CPU status from HSA to optimize the handling of events, profiling, commands, and HSA signals for higher performance.
- Runtime optimization which combines all logic of
WaitAny
in a single processing loop and avoids extra memory allocations or reference counting. The runtime won't spin on the CPU if all events are busy.- Multi-threaded dispatches for performance improvement.
- Command submissions and processing between CPU and GPU by introducing a way to limit the software batch size.
- Switch to
std::shared_mutex
in book/keep logic in streams from multiple threads simultaneously, for performance improvement in specific customer applications.std::shared_mutex
is used in memory object mapping, for performance improvement.Resolved issues
- Race condition in multi-threaded producer/consumer scenario with
hipMallocFromPoolAsync
.- Segmentation fault with
hipStreamLegacy
while using the APIhipStreamWaitEvent
.- Usage of
hipStreamLegacy
in HIP event record.- A soft hang in graph execution process from HIP user object. The fix handles the release of graph execution object properly considering synchronization on the device/stream. The user application now behaves the same with
hipUserObject
on both the AMD ROCm and NVIDIA CUDA platforms.hipfort (0.5.1)
Added
- Support for building with LLVM Flang.
Resolved issues
- Fixed the exported
hipfort::hipsparse
CMake target.ROCm Systems Profiler (0.1.1)
Resolved issues
- Fixed an error when building from source on some SUSE and RHEL systems when using the
ROCPROFSYS_BUILD_DYNINST
option.ROCProfiler (2.0.0)
Changed
- Replaced
CU_UTILIZATION
metric withSIMD_UTILIZATION
for better accuracy.Resolved issues
- Fixed the
VALUBusy
andSALUBusy
activity metrics for accuracy on MI300.ROCprofiler-SDK (0.5.0)
Added
- Support for system-wide collection of SQ counters across all HSA processes.
Changed
rocprofiler_sample_device_counting_service
API updated to return counter output immediately, when called in synchronous mode.ROCm known issues
ROCm known issues are noted on {fab}
github
GitHub. For known
issues related to individual components, review the Detailed component changes.ROCm resolved issues
The following are previously known issues resolved in this release. For resolved issues related to
individual components, review the Detailed component changes.TransferBench packages not functional
Issue with TransferBench packages not being compiled properly has been fixed. For more information, See GitHub issue #4081.
ROCm Compute Profiler CTest failure in CI
When running the ROCm Compute Profiler (
rocprof-compute
) CTest in the Azure CI environment, therocprof-compute
execution test failed. This issue was due to an outdated test file that was not renamed
(omniperf
torocprof-compute
), and theROCM_PATH
environment variable not being set in
the Azure CI environment, resulting in the tool being unable to extract chip information as expected.
This issue has been fixed in the ROCm 6.3.2 release. See GitHub issue #4085.MIVisionX memory access fault in Canny edge detection
An issue where Canny edge detection kernels accessed out-of-bounds memory locations while
computing gradient intensities on edge pixels has been fixed. This issue was isolated to
Canny-specific use cases on Instinct MI300 series accelerators. See GitHub issue #4086.AMD VCN instability with rocDecode
A firmware crash on gfx942 devices when AMD Video Core Next (VCN) was used for rocDecode operations has been resolved.
ROCm upcoming changes
The following changes to the ROCm software stack are anticipated for future releases.
AMDGPU wavefront size compiler macro deprecation
The
__AMDGCN_WAVEFRONT_SIZE__
macro will be deprecated in an upcoming
release. It is recommended to remove any use of this macro. For more information, see AMDGPU
support.HIPCC Perl scripts deprecation
The HIPCC Perl scripts (
hipcc.pl
andhipconfig.pl
) will be removed in an upcoming release.